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74ALVCH16373DTR 数据表 (PDF) - ON Semiconductor

74ALVCH16373DTR Datasheet PDF - ON Semiconductor
部件名 74ALVCH16373DTR
下载  74ALVCH16373DTR 下载

文件大小   143.21 Kbytes
  12 Pages
制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor
功能描述 LOW-VOLTAGE 16-BIT TRANSPARENT LATCH WITH BUS HOLD 1.8/2.5/3.3 V

74ALVCH16373DTR Datasheet (PDF)

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74ALVCH16373DTR Datasheet PDF - ON Semiconductor

部件名 74ALVCH16373DTR
下载  74ALVCH16373DTR Click to download

文件大小   143.21 Kbytes
  12 Pages
制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor
功能描述 LOW-VOLTAGE 16-BIT TRANSPARENT LATCH WITH BUS HOLD 1.8/2.5/3.3 V

74ALVCH16373DTR 数据表 (HTML) - ON Semiconductor

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74ALVCH16373DTR 产品详情

Low-Voltage 16-Bit Transparent Latch with Bus Hold 1.8/2.5/3.3 V (3–State, Non–Inverting)

The 74ALVCH16373 is an advanced performance, non–inverting 16–bit transparent latch. It is designed for very high–speed, very low–power operation in 1.8 V, 2.5 V or 3.3 V systems. The VCXH16373 is byte controlled, with each byte functioning identically, but independently. Each byte has separate Output Enable and Latch Enable inputs. These control pins can be tied together for full 16–bit operation.
The 74ALVCH16373 contains 16 D–type latches with 3–state 3.6 V–tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, (a latch output will change state each time its D input changes). When LE is LOW, the latch stores the information that was present on the D inputs a setup time preceding the HIGH–to–LOW transition of LE. The 3–state outputs are controlled by the Output Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When OE is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches. The data inputs include active bushold circuitry, eliminating the need for external pull–up resistors to hold unused or floating inputs at a valid logic state.

• Designed for Low Voltage Operation: VCC = 1.65 – 3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation:
   3.0 ns max for 3.0 to 3.6 V
   3.9 ns max for 2.3 to 2.7 V
   6.8 ns max for 1.65 to 1.95 V
• Static Drive:
   ±24 mA Drive at 3.0 V
   ±18 mA Drive at 2.3 V
   ±6 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
   Logic State
• IOFF Specification Guarantees High Impedance When VCC = 0 V†
• Near Zero Static Supply Current in All Three Logic States (20 µA)
   Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance:
   Human Body Model >2000 V;
   Machine Model >200 V
• Second Source to Industry Standard 74ALVCH16373




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