[Nanya] Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. Features • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock inputs (CK and CK) • Four internal banks for concurrent operation • Data mask (DM) for write data • DLL aligns DQ and DQS transitions with CK transitions. • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Burst lengths: 2, 4, or 8 • CAS Latency: 2, 2.5 • Auto Precharge option for each burst access • Auto Refresh and Self Refresh Modes • 7.8ms Maximum Average Periodic Refresh Interval • 2.5V (SSTL_2 compatible) I/O • VDDQ = 2.5V ± 0.2V • VDD = 2.5V ± 0.2V • Package : 66pin TSOP-II / 60 balls 0.8mmx1.0mm pitch CSP.
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