General Description
The LVT373 and LVTH373 consist of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in a high impedance state.

Features
■ Input and output interface capability to systems at 5V VCC
■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH373), also available without bushold feature (74LVT373)
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free bus loading
■ Outputs source/sink –32 mA/+64 mA
■ Functionally compatible with the 74 series 373
■ ESD performance:
    – Human-body model > 2000V
    – Machine model > 200V
    – Charged-device model > 1000V