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EP224LC-7 数据表 (PDF) - Altera Corporation

EP224LC-7 Datasheet PDF - Altera Corporation
部件名 EP224LC-7
下载  EP224LC-7 下载

文件大小   398.89 Kbytes
  16 Pages
制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation
功能描述 Classic EPLDs

EP224LC-7 Datasheet (PDF)

Go To PDF Page 下载 数据表
EP224LC-7 Datasheet PDF - Altera Corporation

部件名 EP224LC-7
下载  EP224LC-7 Click to download

文件大小   398.89 Kbytes
  16 Pages
制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation
功能描述 Classic EPLDs

EP224LC-7 数据表 (HTML) - Altera Corporation

Back Button EP224LC-7 Datasheet HTML 1Page - Altera Corporation EP224LC-7 Datasheet HTML 2Page - Altera Corporation EP224LC-7 Datasheet HTML 3Page - Altera Corporation EP224LC-7 Datasheet HTML 4Page - Altera Corporation EP224LC-7 Datasheet HTML 5Page - Altera Corporation EP224LC-7 Datasheet HTML 6Page - Altera Corporation EP224LC-7 Datasheet HTML 7Page - Altera Corporation EP224LC-7 Datasheet HTML 8Page - Altera Corporation EP224LC-7 Datasheet HTML 9Page - Altera Corporation EP224LC-7 Datasheet HTML 10Page - Altera Corporation Next Button 

EP224LC-7 产品详情

General Description
The EPROM-based EP220 and EP224 devices feature a flexible I/O architecture and implement 150 usable (300 available) gates of custom user logic functions. EP220 and EP224 devices can be used as upgrades for high-speed bipolar programmable logic devices (PLDs) or for 74-series LS and CMOS (SSI and MSI) logic devices in high-performance microcomputer systems.

Features
■ High-performance, low-power Erasable Programmable Logic Devices (EPLDs) with 8 macrocells
    – Combinatorial speeds as low as 7.5 ns
    – Counter frequencies of up to 100 MHz
    – Pipelined data rates of up to 115 MHz
    – Maximum 5.5-ns Clock-to-output time; minimum 4.5-ns setup time
■ Replacement or upgrade for 16V8/20V8 PAL and GAL devices
■ Up to 18 inputs (10 dedicated inputs) in EP220, 22 inputs (14 dedicated inputs) in EP224; up to 8 outputs in both EP220 and EP224
■ Macrocells independently programmable for both registered and combinatorial logic
■ Programmable inversion control supporting active-high or activelow outputs
■ Low power consumption
    – Typical ICC = 90 mA at 25 MHz (for -7A speed grades)
    – Quarter-power mode (ICC = 40 mA)
    – Programmable zero-power mode with typical ICC = 50 µA (for -10A and -12 speed grades)
■ Programmable Security Bit for total protection of proprietary designs
■ Low output skew for Clock driver applications
■ 100% generically tested to provide 100% programming yield
■ Software and programming support from Altera and a wide range of third-party tools
■ Available in windowed ceramic and one-time-programmable (OTP) plastic packages
    – 20-pin plastic J-lead package (PLCC)
    – 20-pin ceramic and plastic dual in-line packages (CerDIP and PDIP)
    – 24-pin PDIP
    – 28-pin PLCC




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关于 Altera Corporation


Altera Corporation是美国可编程逻辑设备(PLD)的美国制造商,可重新配置的复杂数字电路。它是在2015年被英特尔公司收购的,现在是英特尔的子公司。

Altera成立于1983年,是可编程逻辑领域中的先驱之一,提供了一系列PLD产品,包括现场可编程的门阵列(FPGA),复杂的可编程逻辑设备(CPLD)和用于数字信号处理和内存的专业芯片接口功能。该公司的产品用于多种应用,包括通信系统,工业自动化,医疗设备和军事系统。

Altera以其在PLD市场的创新而闻名,包括发展高密度FPGA和低功率,高性能CPLD。随着英特尔的收购,Altera继续为其客户提供PLD解决方案,利用世界上最大的技术公司之一的资源和技术。

*此信息仅供一般参考,对于因上述信息造成的任何损失或损害,我们概不负责。




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