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NT5DS64M4AT-75B 数据表 (PDF) - List of Unclassifed Manufacturers

NT5DS64M4AT-75B Datasheet PDF - List of Unclassifed Manufacturers
部件名 NT5DS64M4AT-75B
下载  NT5DS64M4AT-75B 下载

文件大小   1557.12 Kbytes
  78 Pages
制造商  ETC2 [List of Unclassifed Manufacturers]
网页  
标志 ETC2 - List of Unclassifed Manufacturers
功能描述 256Mb Double Data Rate SDRAM

NT5DS64M4AT-75B Datasheet (PDF)

Go To PDF Page 下载 数据表
NT5DS64M4AT-75B Datasheet PDF - List of Unclassifed Manufacturers

部件名 NT5DS64M4AT-75B
下载  NT5DS64M4AT-75B Click to download

文件大小   1557.12 Kbytes
  78 Pages
制造商  ETC2 [List of Unclassifed Manufacturers]
网页  
标志 ETC2 - List of Unclassifed Manufacturers
功能描述 256Mb Double Data Rate SDRAM

NT5DS64M4AT-75B 数据表 (HTML) - List of Unclassifed Manufacturers

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NT5DS64M4AT-75B 产品详情

[Nanya]

Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM.

Features

• Double data rate architecture: two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
• DQS is edge-aligned with data for reads and is centeraligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2, 2.5
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8ms Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.5V ± 0.2V
• VDD = 2.5V ± 0.2V
• -7K parts support PC2100 modules.
    -75B parts support PC2100 modules
    -8B parts support PC1600 modules




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