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CY7C1418KV18-300BZC 数据表 (PDF) - Cypress Semiconductor

CY7C1418KV18-300BZC Datasheet PDF - Cypress Semiconductor
部件名 CY7C1418KV18-300BZC
下载  CY7C1418KV18-300BZC 下载

文件大小   1324.29 Kbytes
  32 Pages
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor
功能描述 36-Mbit DDR II SRAM 2-Word Burst Architecture

CY7C1418KV18-300BZC Datasheet (PDF)

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CY7C1418KV18-300BZC Datasheet PDF - Cypress Semiconductor

部件名 CY7C1418KV18-300BZC
下载  CY7C1418KV18-300BZC Click to download

文件大小   1324.29 Kbytes
  32 Pages
制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor
功能描述 36-Mbit DDR II SRAM 2-Word Burst Architecture

CY7C1418KV18-300BZC 数据表 (HTML) - Cypress Semiconductor

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CY7C1418KV18-300BZC 产品详情

Functional Description
The CY7C1416KV18, CY7C1427KV18, CY7C1418KV18, and CY7C1420KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter.

Features
■ 36-Mbit density (4 M × 8, 4 M × 9, 2 M × 18, 1 M × 36)
■ 333 MHz clock for high bandwidth
■ 2-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
   ❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed systems
■ Synchronous internally self-timed writes
■ DDR II operates with 1.5 cycle read latency when DOFF is asserted HIGH
■ Operates similar to DDR-I device with 1 cycle read latency when DOFF is asserted LOW
■ 1.8 V core power supply with HSTL inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4 V to VDD)
   ❐ Supports both 1.5 V and 1.8 V IO supply
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement




类似零件编号 - CY7C1418KV18-300BZC

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类似说明 - CY7C1418KV18-300BZC

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关于 Cypress Semiconductor


赛普拉斯半导体是一家美国公司,专门从事高性能数字和模拟集成电路(ICS)的设计和制造。
该公司成立于1982年,总部位于美国加利福尼亚州圣何塞。
赛普拉斯(Cypress)提供了广泛的产品,包括微控制器,内存产品,无线连接解决方​​案以及其他数字和模拟IC。
该公司的产品用于各种应用,例如消费电子,汽车系统,工业系统等。
赛普拉斯以其在嵌入式系统领域的混合信号和可编程系统,高质量产品和创新方面的专业知识而闻名。

*此信息仅供一般参考,对于因上述信息造成的任何损失或损害,我们概不负责。




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